How to deliver on time in lower technology nodes?

Over the years, we have seen a wide range of advancements in semiconductor design services. The Semiconductor Industry Association (SIA) announced that the global semiconductor industry posted sales of $468.8 billion in 2018, the highest annual total in industry history and an increase of 13.7%. compared to 2017 sales.

As the demand for semiconductor services continues to increase and the industry witnesses a broader range of technological innovations, we can clearly see a move towards lower geometries (7nm, 12nm, 16nm, etc.). The key drivers behind this trend are the benefits in terms of horsepower, area, and various other features that are possible with lower geometries.

The proliferation of lower geometries has boosted business in several areas, especially in the sectors of mobility, communication, IoT, cloud, AI for hardware platforms (ASIC, FPGA, boards).

Delivering a low-tech design project on time is important in today’s dynamic and competitive marketplace. However, there are many unknowns in the lower geometry that impact the scheduled delivery of the project/product. Taking into account the following elements, it is possible to guarantee the delivery on time in the lower geometry nodes.

1. Cost modeling of lower technology nodes

A chip design lead provides the strong technical leadership required and has overall responsibility for integrated circuit design.

For lower geometry design, engineers must define the activities from specification to silicon, sequence them in the correct order, estimate the resources required, and estimate the time required to complete the tasks. At the same time, they must focus on reducing total system cost while meeting specific service requirements. The following are the actions that engineers can take for cost optimization:

Use multiple patterns

Use appropriate design-for-test (DFT) techniques

Leverage masking, interconnects, and process control

In different design methods because downscaling the nodes is no longer cost effective. For continuous performance improvement along with cost control, some companies are now looking at monolithic 3D ICs instead of a conventional flat implementation, as this can provide 30% power savings, 40% performance increase and reduce cost by 5-10% without switching to a new node.

2. Advanced data analysis for smart chip manufacturing

In the chip manufacturing process, a large volume of data is generated in the manufacturing plant. Over the years, the amount of this data has continued to grow exponentially with each new dimension of technology node. Engineers have played a critical role in generating and analyzing data with the goal of improving performance and predictive maintenance, improving R&D, improving product efficiency, and more.

The application of advanced analytics in chip manufacturing can help improve the quality or performance of individual components, reduce quality assurance testing time, increase throughput, increase equipment availability, and reduce operating costs.

3. Efficient supply chain management

Since new technology is often released faster than the R&D schedule, everyone in the chip manufacturing industry is facing a problem in IC supply chain management. The big question is: how to improve efficiency and profitability in this scenario.

The answer is faster decision making and efficient integration of multiple suppliers, customer requirements, distribution centers, warehouses, and stores so that merchandise is produced with end-to-end supply chain visibility and distributed across the right quantities, at the right time to the customer. correct location to minimize total system cost.

4.Process for timely delivery

Enhanced customer delivery is a critical part of semiconductor design services. It includes setting up order capture to work with orders at runtime, optimizing cloud computing, logistics, and transferring the final product to a customer, while keeping them up-to-date with all the information required in each stage. Full flow planning ensures that critical project deadlines are not missed.

To overcome delays, semiconductor design firms can:

• Minimize the use of custom flows and switch to location and route flows for better physical data path capabilities.

• Establish and adhere to a rapid response time to customer requirements and change requests.

• Get real-time information from specifications to silicon availability in terms of semiconductor design flow, location, reservation, and quantity.

• Ensure collaborative communication between the teams working on the project.

• Focus on criticality analysis: reduce the risk of functional design failures to avoid business interruptions.

• Gain experience using multiple tools to manage the project.

• Embrace better technologies (TSMC, GF, UMC, Samsung), better methodology (low power consumption and high speed performance), better tools (Innovus, Synopsys, ICC2, Primetime, ICV).

How is eInfochips positioned to serve the market?

Whether you want to design innovative products faster, optimize R&D costs, improve time to market, improve operational efficiencies, or maximize return on investment (ROI), eInfochips (an Arrow company) is the partner for suitable design.

eInfochips has worked with many of the leading global companies to contribute more than 500 product designs, with more than 40 million implementations worldwide. eInfochips has a large group of engineers who are specialized in PES services, with a focus on in-depth R&D and new product development.

In order to deliver the product within a short time to market, eInfochips provides ASIC, FPGA and SoC design services based on standard interface protocols. Includes:

1. Front-end (RTL design, verification) and back-end (physical design and DFT) approval services

2. Turnkey design services covering RTL to GDSII and layout design

3. Use of reusable IPs and a framework that helps the company reduce product development time and cost for a faster and more appropriate time to market

This blog was originally published on eInfochips.com.